Fujitsu Intel Xeon 5160 handleiding

Fujitsu Intel Xeon 5160
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Thermal Specifications
86 Dual-Core Intel
®
Xeon
®
Processor 5100 Series Datasheet

6.2.5 THERMTRIP# Signal

Regardless of whether or not Thermal Monitor or Thermal Monitor 2 is enabled, in the
event of a catastrophic cooling failure, the processor will automatically shut down when
the silicon has reached an elevated temperature (refer to the THERMTRIP# definition in
Table 5-1). At this point, the FSB signal THERMTRIP# will go active and stay active as
described in Table 5-1. THERMTRIP# activation is independent of processor activity and
does not generate any bus cycles. Intel also recommends the removal of V
TT
.

6.3 Platform Environment Control Interface (PECI)

6.3.1 Introduction

The introduction of the Dual-Core Intel
®
Xeon
®
Processor 5100 Series marks the
transition from thermal diodes to digital thermal sensors for fan speed control. Digital
Thermal Sensors (DTS) are on-die, analog-to-digital temperature converters calibrated
at the factory for reasonable accuracy to provide a digital representation of relative
processor temperature. Data from the DTS are processed and stored in a processor
register which is queried through the Platform Environment Control Interface (PECI).
PECI is a proprietary one-wire bus interface that provides a communication channel
between Intel processor and chipset components to external thermal monitoring
devices. A topology diagram is given in Figure 6-7. The PECI bus offers:
A wide speed range from 2 Kbps to 2 Mbps.
CRC check byte used to efficiently and automatically confirm accurate data delivery
Synchronization at the beginning of every message minimizes device timing
accuracy requirements
The Platform Environment Control Interface (PECI) bus uses a single wire for self-
clocking and data transfer, and requires no additional control lines. The physical layer
is a self-clocked one-wire bus that begins each bit with a driven, rising edge from an
idle level near zero volts. The duration of the signal driven high depends on whether
the bit value is a logic '0' or logic '1'. PECI also includes variable data transfer rate
established with every message. The single wire interface provides low board routing
overhead for the multiple load connections in the congested routing area near the
processor and chipset components. Bus speed, error checking, and low protocol
overhead provides adequate link bandwidth and reliability to transfer critical device
operating conditions and configuration information.
Note: The PECI interface is disabled by default, and must be enabled through BIOS by setting
PECI_EN (bit 0 of Model Specific Register PECI_CTL at address 05A0h) to 1.
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Bekijk hier gratis de handleiding van de Fujitsu Intel Xeon 5160. Deze handleiding valt onder de categorie Processoren en is door 1 mensen gewaardeerd met een gemiddelde van een 7.5. Deze handleiding is beschikbaar in de volgende talen: Engels. Heeft u een vraag over de Fujitsu Intel Xeon 5160 of heeft u hulp nodig? Stel hier je vraag

Fujitsu Intel Xeon 5160 specificaties

Algemeen
Merk Fujitsu
Model Intel Xeon 5160
Product Processor
Taal Engels
Bestandstype PDF
Processor
Processor socket LGA 771 (Socket J)
Box Nee
Processor cache 4 MB
Basisfrequentie processor 3 GHz
Processorfamilie Intel® Xeon® 5000 reeks
Processor operating modes 32-bit
Front-side bus processor 1333 MHz
Processormodel 5160
CPU multiplier (bus/core ratio) 9
Thermal Design Power (TDP) 80 W
VID Voltage Range 1 - 1.5 V
L2-cache snelheid 3 GHz
Aantal processorkernen 2
Processor lithografie 65 nm
Component voor Server/werkplaats
Processor cache type L2
Eisen aan de omgeving
Maximale temperatuur (in bedrijf) 65 °C
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